This application is based on Japanese Patent Application HEI 11-227768, filed on Aug. 11, 1999, and 2000-213600 filed on Jul. 14, 2000, the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a CCD solid state image pickup device and its manufacture, and more particularly to improvements on a transfer efficiency of electric charges of a solid state image pickup device to be transferred from vertical charge transfer paths to a horizontal charge transfer path.
b) Description of the Related Art
The structure of a general interline CCD solid state image pickup device will be described with reference to FIG. 13, FIGS. 14A and 14B, and FIGS. 15A and 15B.
FIG. 13 is a plan view of a general interline CCD solid state image pickup device, and FIGS. 14A and 14B are schematic cross sectional views illustrating charge transfer in a vertical charge transfer path VCCD and a horizontal charge transfer path HCCD. FIG. 14A shows the structure of the vertical charge transfer path VCCD, and FIG. 14B shows the structure of the horizontal charge transfer path HCCD. FIG. 15A is a schematic cross sectional view showing the structure of a region including a vertical charge transfer channel layer, and FIG. 15B is a schematic cross sectional view showing the structure of a horizontal charge transfer channel layer.
A solid state image pickup device A is formed, for example, in an n-type semiconductor layer 101 formed on a semiconductor substrate of silicon or the like.
In this n-type semiconductor layer 101, pixels 103, vertical charge transfer paths 105, a horizontal charge transfer path 107 and an output amplifier 111 are formed. A plurality of pixels 103 are formed on this n-type semiconductor layer 101, regularly disposed in vertical and horizontal directions.
Each pixel 103 includes a photodiode (photoelectric conversion element) 103a and a transfer gate 103b. 
The photodiode 103a converts received light into electric charges and stores the electric charges.
The transfer gate 103b is a read gate which is used when electric charges stored in the photodiode 103a are read.
Along each pixel column with a plurality of pixels 103 being regularly disposed in the vertical direction, one vertical charge transfer channel region 105 is disposed which is made of, for example, an n-type semiconductor layer.
Along the lower ends of a plurality of vertical charge transfer channel layers 105, a horizontal charge transfer channel layer 107 is disposed which is made of, for example, an n-type semiconductor layer.
A p-type semiconductor layer 108 is formed surrounding the vertical charge transfer layers 105 and horizontal charge transfer channel layer 107.
As shown in FIG. 14A, the p-type semiconductor layer 108 is formed on one surface of the n-type semiconductor layer 101. The vertical charge transfer channel layer 105 is formed in this p-type semiconductor layer 108. The vertical charge transfer channel layer 105 is made of a semiconductor layer having generally a uniform n-type (first conductivity type) impurity concentration.
Two charge transfer electrodes 121 per one pixel row are formed on the vertical charge transfer channel layer 105. Voltages "PHgr"1 to "PHgr"4 are applied to adjacent four charge transfer electrodes 121.
The vertical charge transfer path VCCD is constituted of the vertical charge transfer channel layer 105 and charge transfer electrodes 121. Four-phase drive voltages V1 to V4 are applied to four vertical transfer electrodes adjacent in the vertical direction. With this four-phase driving, charges in the vertical charge transfer channel layer 105 are transferred toward the horizontal charge transfer channel layer 107.
As shown in FIG. 14B, the p-type semiconductor layer 108 continuous with the p-type semiconductor layer 108 shown in FIG. 14A is formed on one surface of the n-type semiconductor layer 101. The horizontal charge transfer channel layer 107 is formed in the p-type semiconductor layer 108. The horizontal charge transfer channel layer 107 is formed by disposing first and second horizontal charge transfer channel layers 107-1 and 107-2 having different n-type (first conductivity type) concentrations. The n-type impurity concentration of the first horizontal charge transfer channel layer 107-1 is higher than that of the second horizontal charge transfer channel layer 107-2. Alternatively, the second horizontal charge transfer channel layer 107-2 may be doped with first conductivity type impurities having the same concentration as the first horizontal charge transfer channel layer 107-1 and with impurities of a second conductivity type opposite to the first conductivity type. By doping the impurities of the opposite conductivity type, the effective first conductivity type impurity concentration is lowered. A potential profile of a two-stage structure having a potential barrier on the right side is repetitively formed from right to left in FIG. 14B. Two potential structures each having a potential barrier and a potential well are disposed in the horizontal direction to constitute one unit of charge transfer (hereinafter called xe2x80x9cone packetxe2x80x9d).
A plurality of charge transfer electrodes 123 are formed on the horizontal charge transfer channel layer 107 in position alignment with the first and second horizontal charge transfer channel layers 107-1 and 107-2. A first transfer electrode 123-1 made of first layer polysilicon and a second transfer electrode 123-2 made of second layer polysilicon are alternately disposed side by side in the horizontal direction.
For example, the first transfer electrode 123-1 is formed on the first horizontal charge transfer channel layer 107-1, and the second transfer electrode 123-2 is formed on the second horizontal charge transfer channel layer 107-2.
Adjacent two charge transfer electrodes 123-1 and 123-2 are connected in common, and the next adjacent two charge transfer electrodes 123-1 and 123-2 are also connected in common. Voltages "PHgr"1 and "PHgr"2 are alternately applied to these common connections. This structure is repeated in the horizontal direction. With two-phase driving of "PHgr"1 and "PHgr"2, charges in the horizontal charge transfer channel layer 107 are transferred left in the horizontal direction.
The vertical charge transfer channel layers 105 are electrically connected to every second first horizontal charge transfer channel layers (potential well) 107-1 formed in the horizontal charge transfer channel layer 107.
As shown in FIG. 15A, the p-type semiconductor layer 108 is formed in the n-type semiconductor layer 101. The vertical charge transfer channel layer 105 is formed in the p-type semiconductor layer 108.
As shown in FIG. 15B, the p-type semiconductor layer 108 is formed in the n-type semiconductor layer 101. The horizontal charge transfer channel layer 107 is formed in the p-type semiconductor layer 108.
In FIG. 13, the p-type semiconductor layers 108 are indicated by one-dot chain lines. The p-type semiconductor layers 108 are formed in areas including the vertical charge transfer channel layers 105 and horizontal charge transfer channel layer 107 by using the same process and have the same depth and impurity concentration.
The cross section of the first horizontal charge transfer channel layer 107-1 having generally the same impurity concentration as that of the vertical charge transfer channel layer 105 is shown in FIG. 15B.
As indicated by a broken line in FIG. 14A, a deep depletion layer is formed in the vertical charge transfer channel layer under the electrodes ("PHgr"3 and "PHgr"4) applied with a voltage HIGH, the depletion layer extending deep to the p-type semiconductor layer 108. Another depletion layer indicated by the broken line is also formed in the vertical charge transfer channel layer under the electrodes ("PHgr"1 and "PHgr"2) applied with a voltage LOW in the direction toward the p-type semiconductor layer 108. However, this depletion layer is shallower than that applied with the HIGH voltage. Namely, the end of the depletion layer is shallow. By switching between the voltages HIGH and LOW to be applied to "PHgr"1 to "PHgr"4, charges can be transferred toward the horizontal charge transfer channel by four-phase driving.
As indicated by a broken line in FIG. 14B, a deep depletion layer extends from the first horizontal charge transfer channel 107-1 under the electrode ("PHgr"2) applied with the voltage HIGH deep into the p-type semiconductor layer 108. Another depletion layer is relatively shallow which extends from the second horizontal charge transfer channel layer 107-2 under the electrode ("PHgr"1) applied with the voltage LOW. By switching between the voltages HIGH and LOW to be applied to "PHgr"1 and "PHgr"2, charges can be transferred in the horizontal charge transfer channel in the horizontal direction (left in FIG. 14B) by two-phase driving.
As shown in FIG. 13, in the solid state image pickup device, a number of vertical charge transfer channel layer 105 are connected to the horizontal charge transfer channel layer 107. In order to efficiently transfer charges sequentially supplied from the vertical charge transfer channel layers 105 in the horizontal direction, it is important to speed up the charge transfer speed of the horizontal charge transfer channel layer 107.
For the higher charge transfer speed of the horizontal charge transfer channel layer 107, the amplitudes of voltages applied to the electrodes 123 are made large (a difference between voltages applied to "PHgr"1 and "PHgr"2 is made large).
However, if the amplitudes of voltages applied to the electrodes 123 are made too large (if a difference between voltages applied to "PHgr"1 and "PHgr"2 is made too large), the end of the depletion layer indicated by the broken line in FIG. 14B extends too deep and may reach the interface between the p-type semiconductor layer 108 and n-type semiconductor layer 101. If the end of the depletion layer reaches the interface, electrons during transfer may be pulled into the n-type semiconductor layer 101 and cannot be transferred efficiently. If the end of the depletion layer reaches near the interface although it does not reach the interface, there is a high probability that electrons enter the n-type semiconductor layer 101 by punch through.
It is an object of the present invention to improve a transfer efficiency of charges in the horizontal charge transfer channel.
According to one aspect of the present invention, there is provided a solid state image pickup device comprising: a semiconductor substrate; a semiconductor layer of a first conductivity type formed in the semiconductor substrate; a plurality of photoelectric conversion elements formed in the semiconductor layer regularly in vertical and horizontal directions; a plurality of first semiconductor layers of a second conductivity type opposite to the first conductivity type, the first semiconductor layer being formed in the semiconductor layer along a photoelectric conversion element column having the photoelectric conversion elements regularly disposed in the vertical direction, and extending in the vertical direction and protruding from the photoelectric conversion element column; a second semiconductor layer of the second conductivity type formed in the semiconductor layer, the second semiconductor layer extending in the horizontal direction and having an opposing end which is positioned near at one end of the photoelectric conversion element column of each of the first semiconductor layers and faces the one end spaced by a distance L from the one end; a horizontal charge transfer channel layer of the first conductivity type formed in the second semiconductor layer and extending in the horizontal direction; a plurality of vertical charge transfer channel layers of the first conductivity type each extending in the vertical direction in a corresponding one of the first semiconductor layers toward the horizontal charge transfer channel layer and protruding from the one end to couple the horizontal charge transfer channel layer; and a third semiconductor layer of the second conductivity type formed between the one ends and the opposing side, the third semiconductor layer of the second conductivity type having an impurity concentration lower than a higher one of impurity concentrations of the first and second semiconductor devices of the second conductivity type.
According to another aspect of the present invention, there is provided a method of manufacturing a solid state image pickup device comprising the steps of: (a) forming a first mask on a semiconductor layer of a first conductivity type formed on a principal surface of a semiconductor substrate, the first mask having a first opening extending in a horizontal direction in a plane of the principal surface; (b) forming a second semiconductor layer of a second conductivity type opposite to the first conductivity type in the semiconductor layer in a region corresponding to the first opening, by using the first mask, the second semiconductor layer extending in the horizontal direction; (c) forming a second mask on the semiconductor layer, the second mask having a plurality of second openings extending in a vertical direction in the plane of the principal surface, one end of each second opening being adjacent to a first position defined by one end of the first opening and aligned with a second position spaced from the first position by a distance Lm, the one end of each second opening facing the one end of the first opening; (d) forming a plurality of first semiconductor layers of the second conductivity type in the semiconductor layer in regions corresponding to the second openings, by using the second mask; (e) forming a horizontal charge transfer channel layer of the first conductive type in the second semiconductor layer, the horizontal charge transfer channel layer extending in the horizontal direction; (f) forming a plurality of vertical charge transfer channel layers of the first conductivity type, each of the vertical charge transfer channel layers extending in the second conductivity layer toward the horizontal charge transfer channel layer and protruding from the first position to couple the horizontal charge transfer channel layer; g) forming a third semiconductor layer of the second conductivity type in a region between the first and second positions; and (h) forming a plurality of photoelectric conversion elements regularly disposed in the vertical direction along the plurality of vertical charge transfer channel layers.
It is possible to raise a transfer speed (transfer efficiency) of charges in the horizontal charge transfer path. It is possible to prevent the transfer efficiency of charges to be transferred from the vertical charge transfer paths to the horizontal charge transfer path from being lowered.